The present invention relates to semiconductor devices and methods for fabricating the same, and particularly relates to gate insulating films for metal-oxide semiconductor (MOS) transistors and methods for fabricating the gate insulating films.
In a complementary MOS (CMOS) transistor, for example, among MOS transistors that are typical MOS-type devices, a transistors for high speed driving (hereinafter, also referred to as a high-speed transistor) required to have a relatively thin gate insulating film and a transistor for high breakdown voltage (hereinafter, also referred to as a high-breakdown-voltage transistor) used for input/output signals with relatively high voltages and required to have a relatively thick gate insulating film are formed on a single semiconductor substrate. The gate insulating film of the high-speed transistor needs to have a thickness of about 1 nm to about 3 nm and also imperatively needs to have high reliability in resistance to dielectric breakdown and a low leakage current property.
In CMOS transistors, a dual-gate structure in which boron (B) is used as a dopant for a p-type gate electrode of a p-transistor and phosphorus (P) is used as a dopant for an n-type gate electrode of an n-transistor has been adopted. In this case, B as a p-type dopant has a diffusion coefficient larger than that of P as an n-type dopant, so that B diffuses in a gate insulating film of a high-speed transistor to reach the channel region through processes such as heat treatment during and after formation of the transistor. Such diffusion of B is called “permeation” and greatly changes the threshold voltage of the transistor. In addition, this B permeation becomes more pronounced as the thickness of the gate insulating film is reduced. The B permeation is conspicuous especially when silicon dioxide (SiO2) is used for the gate insulating film. The reduction of thickness of the gate insulating film causes gate leakage current to increase. Specifically, when a SiO2 film with a thickness of 3 nm or less is used as a gate insulating film, direct tunnel current is dominant, resulting in especially noticeable increase of gate leakage current.
As described above, when a SiO2 film is used as a thin gate insulating film of a high-speed transistor, neither B permeation nor increase of gate leakage current is suppressed.
In view of this, oxynitride films (silicon oxynitride films) to which nitrogen is introduced have begun to be used as gate insulating films (see, Japanese Unexamined Patent Publication (Kokai) No. 2003-347423).
FIGS. 7A through 7D and FIGS. 8A through 8D are cross-sectional views illustrating respective process steps of a conventional method for fabricating a semiconductor device (a CMOS transistor) using thermal oxynitridation so as to introduce nitrogen into gate insulating films.
First, as shown in FIG. 7A, a semiconductor substrate 100 in which a first p-well 101, a first n-well 102, a second p-well 103 and a second n-well 104 are formed is subjected to thermal oxidation, thereby forming a first insulating film 106 on the wells 101 through 104. At this time, isolations 105 are provided between the wells 101 through 104 in the semiconductor substrate 100.
Next, as shown in FIG. 7B, a first photoresist film 107 is formed on a portion of the first insulating film 106 located on the first p-well 101 and the first n-well 102. Then, wet etching is performed using the first photoresist film 107 as a mask, thereby selectively removing a portion of the first insulating film 106 located on the second p-well 103 and the second n-well 104. In other words, the first insulating film 106 remains on the first p-well 101 and the first n-well 102.
Then, as shown in FIG. 7C, the semiconductor substrate 100 is subjected to heat treatment in an atmosphere containing nitrogen such as a nitrogen monoxide (NO) gas or a nitrous oxide (dinitrogen monoxide) (N2O) gas. Accordingly, a first gate insulating film 109 is formed on the first p-well 101 and the first n-well 102 out of the first insulating film 106. The first gate insulating film 109 includes a nitridation region 108 having a nitrogen concentration peak at the interface between the first gate insulating film 109 and the semiconductor substrate 100. In addition, a second gate insulating film 110 having a thickness smaller than that of the first gate insulating film 109 is formed on the second p-well 103 and the second n-well 104. As the first gate insulating film 109, the second gate insulating film 110 also includes a nitridation region 108 having a nitrogen concentration peak at the interface between the second gate insulating film 110 and the semiconductor substrate 100.
The nitridation regions are herein regions having relatively high nitrogen concentrations including nitrogen concentration peaks.
Then, as shown in FIG. 7D, a silicon film 111 is deposited over the semiconductor substrate 100 on which the first gate insulating film 109 and the second gate insulating film 110 are formed. Thereafter, as shown in FIG. 8A, a second photoresist film 112 is formed to cover portions of the silicon film 111 respectively located above the first n-well 102 and the second n-well 104. Subsequently, ions of an n-type dopant (impurity) are selectively implanted in portions of the silicon film 111 respectively located above the first p-well 101 and the second p-well 103 by using the second photoresist film 112 as a mask, thereby forming an n-type silicon film 113.
Thereafter, as shown in FIG. 8B, a third photoresist film 114 is formed to cover the portions of the silicon film 111 respectively located above the first p-well 101 and the second p-well 103. Then, ions of a p-type dopant are selectively implanted in the portions of the silicon film 111 respectively located above the first n-well 102 and the second n-well 104 by using the third photoresist film 114 as a mask, thereby forming a p-type silicon film 115.
Subsequently, as shown in FIG. 8C, the n-type silicon film 113 and the p-type silicon film 115 are patterned into gate electrode shapes, thereby forming n-type conductor parts (i.e., a first n-type gate electrode 116 and a second n-type gate electrode 118) out of the n-type silicon film above the first p-well 101 and the second p-well 103, respectively, and also forming p-type conductor parts (i.e., a first p-type gate electrode 117 and a second p-type gate electrode 119) out of the p-type silicon film above the first n-well 102 and the second n-well 104, respectively. The first gate insulating film 109 is interposed between each of the first n-type gate electrode 116 and the first p-type gate electrode 117 and the semiconductor substrate 100. The second gate insulating film 110 is interposed between each of the second n-type gate electrode 118 and the second p-type gate electrode 119 and the semiconductor substrate 100.
Then, as shown in FIG. 8D, source/drain regions 120 made of an n-type doped layer are formed at both sides of the first n-type gate electrode 116 in the first p-well 101 and at both sides of the second n-type gate electrode 118 in the second p-well 103. In addition, source/drain regions 121 made of a p-type doped layer are formed at both sides of the first p-type gate electrode 117 in the first n-well 102 and at both sides of the second p-type gate electrode 119 in the second n-well 104.
FIGS. 9A through 9D, FIGS. 10A through 10C and FIGS. 11A and 11B are cross-sectional views illustrating respective process steps of a conventional method for fabricating a semiconductor device (a CMOS transistor) using plasma nitridation so as to introduce nitrogen into gate insulating films.
First, as shown in FIG. 9A, a semiconductor substrate 200 in which a first p-well 201, a first n-well 202, a second p-well 203 and a second n-well 204 are formed is subjected to thermal oxidation, thereby forming a first insulating film 206 on the wells 201 through 204. At this time, isolations 205 are provided between the wells 201 through 204 in the semiconductor substrate 200.
Next, as shown in FIG. 9B, a first photoresist film 207 is formed on a portion of the first insulating film 206 located on the first p-well 201 and the first n-well 202. Then, wet etching is performed using the first photoresist film 207 as a mask, thereby selectively removing a portion of the first insulating film 206 located on the second p-well 203 and the second n-well 204. In other words, the first insulating film 206 remains on the first p-well 201 and the first n-well 202.
Then, as shown in FIG. 9C, the semiconductor substrate 200 is subjected to thermal oxidation, thereby forming a second insulating film 208 out of the first insulating film 206 on the first p-well 201 and the first n-well 202 and also forming a third insulating film 209 with a thickness smaller than that of the second insulating film 208 on the second p-well 203 and the second n-well 204.
Thereafter, as shown in FIG. 9D, the entire surfaces of the second insulating film 208 formed on the first p-well 201 and the first n-well 202 and the third insulating film 209 formed on the second p-well 203 and the second n-well 204 are exposed to nitrogen plasma. Accordingly, a first gate insulating film 211 is formed on the first p-well 201 and the first n-well 202 and a second gate insulating film 212 having a thickness smaller than that of the first gate insulating film 211 is also formed on the second p-well 203 and the second n-well 204. Each of the first gate insulating film 211 and the second gate insulating film 212 includes a nitridation region 210 having a nitrogen concentration peak at the surface of the first or second gate insulating film 211 or 212.
Subsequently, as shown in FIG. 10A, a silicon film 213 is deposited over the semiconductor substrate 200 on which the first gate insulating film 211 and the second gate insulating film 212 are formed. Thereafter, as shown in FIG. 10B, a second photoresist film 214 is formed to cover portions of the silicon film 213 respectively located above the first n-well 202 and the second n-well 204. Subsequently, ions of an n-type dopant are selectively implanted in portions of the silicon film 213 located above the first p-well 201 and the second p-well 203 by using the second photoresist film 214 as a mask, thereby forming an n-type silicon film 215.
Thereafter, as shown in FIG. 10C, a third photoresist film 216 is formed to cover portions of the silicon film 213 respectively located above the first p-well 201 and the second p-well 203. Then, ions of a p-type dopant are selectively implanted in portions of the silicon film 213 respectively located above the first n-well 202 and the second n-well 204 by using the third photoresist film 216 as a mask, thereby forming a p-type silicon film 217.
Subsequently, as shown in FIG. 11A, the n-type silicon film 215 and the p-type silicon film 217 are patterned into gate electrode shapes, thereby forming n-type conductor parts (i.e., a first n-type gate electrode 218 and a second n-type gate electrode 220) out of the n-type silicon film above the first p-well 201 and the second p-well 203, respectively, and also forming p-type conductor parts (i.e., a first p-type gate electrode 219 and a second p-type gate electrode 221) out of the p-type silicon film above the first n-well 202 and the second n-well 204, respectively. The first gate insulating film 211 is interposed between each of the first n-type gate electrode 218 and the first p-type gate electrode 219 and the semiconductor substrate 200. The second gate insulating film 212 is interposed between each of the second n-type gate electrode 220 and the second p-type gate electrode 221 and the semiconductor substrate 200.
Thereafter, as shown in FIG. 11B, source/drain regions 222 made of an n-type doped layer are formed at both sides of the first n-type gate electrode 218 in the first p-well 201 and at both sides of the second n-type gate electrode 220 in the second p-well 203. In addition, source/drain regions 223 made of a p-type doped layer are formed at both sides of the first p-type gate electrode 219 in the first n-well 202 and at both sides of the second p-type gate electrode 221 in the second n-well 204.